Synthesis of Asynchronous VLSI Circuits

摘要

With chip size reaching one million transistors. the complexity of VLSI algorithms-i.e., algorithms implemented as a digital VLSI circuit-is approaching that of software algorithms i.e., algorithms implemented as code for a stored-program computer. Yet design methods for VLSI algorithms lag far behind the potential of the technology. Since a digital circuit is the implementation of a concurrent algorithm, we propose a concurrent programming approach to digital VLSI design. The circuit to be designed is first implemented as a concurrent program that fulfills the logical specification of the circuit. The program is then compiled manually or automatically-into a circuit by applying semantic-preserving program transformations. Hence, the circuit obtained is correct by construction. The main obstacle to such a method is finding an interface that provides a good separation of the physical and algorithmic concerns. Among the physical parameters of the implementation, timing is the most difficult to isolate from the logical design, because the timing properties of a circuit are essential not only to its real time behavior but also to its logical correctness if the usual synchronous techniques are used to implement sequencing. For this reason, delay. insensitive' techniques are particularly attractive for VLSI synthesis. A circuit is delay- insensitive when its correct operation is independent of any assumption on delays in operators and wires except that the delays be finite. Such circuits do not use a clock signal or knowledge about delays. Let us clarify a matter of definitions right away: It has been proved in that the class of entirely delay- insensitive circuits is very limited. Different asynchronous techniques distinguish themselves in the choice of the compromises to delay-insensitivity.