Design, Construction, And Testing Of A Reduced-Scale Cascaded Multi- Level Converter

摘要

The main focus in the design of the next generation combatant, DD(X), is the US Navy's proposed Integrated Power System (IPS) which includes an all- electric propulsion drive system. The reduction of current waveform harmonics is critical in combatant propulsion systems such as the IPS. One method of reducing the current harmonics is to utilize a multi-level converter topology. The multi- level converter, as compared to a standard converter, features low dv/dt losses and low switching losses. This thesis examines the design, construction and testing of two multi-level converters operated in tandem, called a Cascaded Multi-Level Converter (CMLC). A digital logic switching circuit is designed and constructed to control the CMLC during the operational testing phase. The CMLC is demonstmted in a three-phase high-voltage configuration with 178.5 V zero-to- peak voltage, 2.10 A zero-to-peak current achieved using an R-L load.