Pipelined Delta Sigma Modulator Analog to Digital Converter for SOC Applications

摘要

A two-stage Pipelined Delta Sigma Modulator analog-to-digital converter is presented for broad band, high resolution System-on-a-Chip (SOC) applications. Input bandwidth is 62.5 MHz and the sampling frequency of 1 GHz results in an oversampling ratio of 8, and a 12-bit resolution with a 50 MHz input.