FPGA Based Compensation Method for Correcting Distortion in Voltage Inverters

摘要

This thesis presents a method to compensate for the blanking time distortion in Space Vector Modulated (SVM) voltage source inverters. Blanking time distortion is caused by the delay inserted to prevent the short circuit that would occur if the two transistors in the same inverter leg are both on at the same time. This delay produces harmonic distortion and non-linearity when two-switch phase legs are used in inverters to generate sinusoidal voltages for various types of AC loads. The approach in this thesis uses a Field Programmable Gate Array to create a pulse by pulse compensation technique that adjusts the symmetric SVM pulses in an attempt to eliminate the voltage distortion caused by the blanking time effect. This technique is evaluated through simulation and experimental results. This thesis proves that the delay caused by the insertion of blanking time can be compensated using a Field Programmable Gate Array and that the blanking time delay is not the dominant source of the 5th and 7th lower order harmonic distortion in voltage source inverters at low voltages.