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A Voltage Controlled Delay Generator,

机译:压控延迟发生器,

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A voltage controlled delay generator is described such as to permit sampling techniques to be used to give improvements in signal/noise ratio of experimental,repetitive,waveforms. The use of a slowly rising linear ramp voltage to provide a continuously variable delay of a pulse relative to a clock pulse provided a significant increase in the accuracy of sampling over a previous scheme which relied upon a mechanical method to control the variable delay potentiometer of a pulse generator. A voltage versus time ramp in excess of one hour is possible by using pulses to control the charging rate of a capacitor connected in an Insulated Gate Field Effect Transistor circuit. (Author)

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