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Expansion and Compression Buffers for the Phase II DSCS TDMA. Design Plan. Exhibits I, III, and IV

机译:第二阶段DsCs TDma的扩展和压缩缓冲器。设计方案。展品I,III和IV

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The design plan, which consists of four parts, documents the design information pertaining to the recommended expansion (or receive) and compression (or transmit) buffers for DSCS 2 TDMA. Exhibit 1 is the functional specification in which the relaton between the expansion and compression buffers and the TDMA system are established. In this context the logical, physical, and operational aspects of the buffer are specified. Exhibit 2 (separately bound) provides the logic design details of the data flow units specified in Exhibit 1. The component list is given in Exhibit 3 and identifies critical components and vendor sources. Exhibit 4 shows the recommended 15-month development plan for an advanced development model of the buffer. (Author)

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