Fault Detection Methods in Combinational Digital Logic Networks

摘要

The ability to test a digital network as simply as possible has become quite important recently due to advances in integrated circuit technology and the consequent increases in the complexity of the networks being produced. The paper presents several existing methods of 'fault detection test generation'. A new approach to the problem of finding a minimal test set is then presented. The test set is obtained by solving a set of equations which are obtained directly from the network. It is shown that the solutions to these equations constitute a complete test set both for a nonreconvergent fanout network and for a reconvergent fanout network. A general solution procedure is presented which will generate a minimal test set for any network. An algorithm for generating a minimal test set for a nonreconvergent fanout network is also presented. (Author)