Discrete-Control Correction: A Technique for the Synchronization of Digital Communication Networks.

摘要

In a digital communication network the transmission and detection of digital data at each node is controlled by a local clock which supplies the reference timing. Each node also uses buffers on its incoming links to allow for delay and frequency variations. If all the clocks are not in synchronism there will be an eventual overflow or depletion of some of the buffers causing loss of information and hence it is desirable to have the clocks run synchronously. This will also lead to minimizing of buffer capacities. This work examines a method of synchronizing nodal clocks in which periodic corrections are made to each clock based upon changes in local buffer levels. Conditions are derived under which synchronization can be achieved. Explicit formulae have been derived for the frequency of synchronism and steady-state buffer levels. It is further shown that in case of failures of some of the nodes the remaining subnetwork or networks attain synchronism by themselves. All the theoretical results have been verified by software simulation as well as actual hardware implementation.