Design of Radiation Hardened MNOS Memory.

摘要

This final report covers work performed in designing a CMOS/SOS memory subsystem based upon given specifications for a 256-bit memory chip. The subsystem interfaces with the Survivable MOS Array Computer (SMARC). Logic design and interconnection for the subsystem are presented, as are the designs and specifications for the three chip types which satisfy all subsystem functions. In addition, the report presents estimates of the producibility and reliability for these chips for both conventional and hardened gate insulators. (Author)