Signal Processor for Binary Phase Coded CW Radar

摘要

This report documents a study of signal processors for a binary phase coded CW radar, where a maximum-length shift register-generated sequence is used for phase modulation. Following a brief review of phase coded CW radars and the problems associated with such radars, several analog, digital and hybrid signal processor configurations are proposed. The advantages and drawbacks of each configuration are discussed. In order to evaluate the performance of the proposed processors, digital computer simulations of the input signal and the processors are developed. These simulations are used to demonstrate the feasibility of digital processing in spite of the large dynamic range. (Author)