Generalized Cyclic Codes Finite Field Arithmetic. Volume III.

摘要

The implementation of finite field arithmetic processing elements in charge-coupled device technology for cyclic error coding is investigated. The strong coupling between the capabilities of the multiple signal level charge-coupled device delay line and the structures needed for nonbinary finite field arithmetic algorithms is shown to have a potential for realizing resource efficient error control coding computational hardware. Laboratory results are described, and recommendations are made in areas where device characteristics require improvement to better meet the needs of the coding structures. (Author)