Test Procedures for Semiconductor Random Access Memories

摘要

Currently available memory testing algorithms were reviewed and evaluated to assess their inadequacies in testing large scale integrated circuit random access memories (RAMs). Categories of functional faults were proposed to include several types of coupling faults. A neighborhood for pattern sensitive faults was defined. A fault model for stuck-at failures in dynamic RAMs was derived, as were requirements to detect abnormal timing parameters. Procedures to detect the following classes of faults were then developed: (1) Functional faults, (2) neighborhood pattern sensitive faults, (3) stuck-at faults in dynamic RAMs, and (4) abnormal access times. (Author)