Discrete Address Beacon System (DABS) Receiver and Air Traffic Control Radar Beacon System (ATCRBS) and DABS Processor Subsystem Tests

摘要

This report describes the subsystem interrogator and processor tests conducted by the Federal Aviation Administration (FAA) Technical Center on the engineering laboratory model of the Discrete Address Beacon System (DABS). These tests were conducted to determine the performance of the multichannel receiver and the Air Traffic Control Radar Beacon System (ATCRBS) and DABS processors. These performance test results supplement the functional subsystem testing performed by Texas Instruments, Incorporated during the factory tests. The results of the receiver tests were used to determine the operating parameters and performance of the monopulse receiver and the operating characteristics of the video quantizer. The ATCRBS reply processor tests identified the static performance and characteristics of the variable parameters in this unit. The DABS reply processor tests defined the performance of the critical elements in the DABS processor. These elements were the video digitizer, the message bit and monopulse processing, and the error detection and correction. Identification and optimization of the characteristics of the variable parameters of this unit were determined. It was concluded that the subsystems tested met the requirements specified in the DABS engineering requirement (ER) FAA-ER-240-26. (Author)