Investigation of Silicon CCD Delay Lines

摘要

The primary objectives of this contract include the analysis, design, and development of advanced CCDs with input and output circuitry as well as delay stages capable of operation at 100 MHz and above clock frequency. A high speed 256 stage CCD delay line with high frequency input and output circuits was designed. The device, circuit and process designs adopted emphasize future growth potential such that performance characteristics may be extended to much higher operating frequencies.