Charge Domain Filters for Enhanced Monolithic Signal Processing.

摘要

The Charge Domain Device (CDD) concept in sampled analog signal processing on a chip was investigated both theoretically and experimentally. The basic operations required for signal processing functions were evaluated, and new structures were discovered which yield an improved level of design flexibility. The physical limitations of the charge domain approach and their effect on overall device performance were determined. In addition to numerous test structures, which were fabricated to evaluate new and improved device structures, design methodologies and tools useful for both mathematical design and structural optimization were developed. An 8-pole narrowband bandpass filter has been designed, fabricated and tested in order to demonstrate the wide range of capabilities of charge domain devices. The experimental characteristics of a filter having a bandwidth of 1/100 of the clocking frequency and over 65 dB passband-to-stopband ratio exemplify these characteristics and verify the utility of the design tools for the program. Design concepts for digital control of filter coefficients - an initial goal - were also developed. This permits a single generic chip type to be used in a large number of applications and opens the door for applications requiring high speed adaptive processes. Test chips have been fabricated and evaluated which demonstrate these concepts. Further capabilities of charge domain filters are discussed and several applications examples for this technology are described. The potential now exists for incorporating higher performance, higher speed signal processing systems on a chip.