Functional Testing of LSI/VLSI (Very Large Scale Integration) Digital Systems

摘要

Due to the advances in the integrated circuit (IC) technology, more and more components are being fabricated into a tiny IC chip. Since the number of pins on each chip is limited by the physical size of the chip, the problem of testing becomes more difficult than ever, especially in the VLSI(Very Large Scale Integration) chips. This problem is aggravated by the fact that, in nearly all cases, integrated circuit manufacturers are not willing to release the detailed circuit diagram of the IC chip to the users. Yet, as users of the IC chips, to make sure that the implemented system is reliable, we need to test the IC chips and the systems made of the interconnection of these chips. The purpose of this project is to find efficient algorithms for testing LSI/VLSI chips and LSI/VSLI-based systems. As a result of the rapidly increasing complexity of modern digital LSI/VLSI systems, functional testing is attracting more attention than ever not only in the computer manufacturing industry but also in the diversified potential applications. Functional testing uses a representation of a digital system higher than the gate-level testing. In functional testing, functional faults with respect to the functional specification (e.g., addition operation in a processor) are tested instead of a signal faults (e.g., a line stuck-at logical 0) in the circuit representation. The purpose of functional testing is to validate correct functional operations of digital systems according to their specifications.