LSI/VLSI (Large Scale Integrated/Very Large Scale Integrated) Ion Implanted Planar GaAs IC Processing

摘要

The scope of this program was two-fold: (1) to complete and stabilize the development of a planar fabrication process for high speed digital integrated circuits on 3-inch GaAs wafers, and (2) to utilize gate arrays up to the 1k equivalent gate level as the demonstration circuits for this process development. In addition to optimizing equipment and handling techniques for 3-inch GaAs wafers, the process development task concentrated on test chip characterizations, threshold voltage uniformity control, and materials evaluation. Piezoelectrically generated device non-uniformities were a primary consideration during this time. The gate array development involved two masked sets. The first was used to establish process and design criteria for gate arrays, as well as to fabricate a 5 x 5 multiplier. The second mask set was an extension of the previous work, and was used to fabricate gate arrays of the 1k equivalent gate complexity. The Mayo Foundation provided the expertise for auto-routing and personalization techniques. (Author)