VLSI (Very Large Scale Integration) Process Problem Diagnosis and Yield Prediction: A Comprehensive Test Structure and Test Chip Design Methodology

摘要

A comprehensive test chip has been designed for fabrication line monitoring, process problem diagnosis, and yield modeling of a two layer metal, oxide isolated, N-well CMOS process. The design philosophy emphasizes global optimization of test structure choices and sizes necessary for sufficiently sensitive detection and unambiguous determination of functional location and densities of process related yield detractors. The test chip has been designed to accompany a microprocessor chip, and will be used to predict its yield. This presentation will describe the salient features of the optimized test structures and the systematic design methodology which emphasizes (i) test structure selection strategy, (ii) test structure sizing, (iii) test chip layout, and (iv) applications to yield prediction based on the elemental defect densities extracted from the defect locator test structures.