Hardware Implementation of a Concatenated Encoder/Decoder

摘要

This study describes the hardware implementation of a concatenated error correcting encoder/decoder. Individual burst and random error correcting coders were implemented using standard TTL integrated circuits and Z-80 microprocessors. The circuits handle input and output operations with a three line handshake. Thus, data transfer between circuits is asynchronous, and the coders may be concatenated in any order. Reed-Solomon, BCH, Golay, interleaving, and convolutional codes were considered. Of these codes, the BCH encoder/decoder, the Golay encoder/decoder, the interleaver/deinterleaver, and the convolutional encoder were all implemented in hardware. The Reed-Solomon encoder/decoder and the convolutional decoder will be implemented in a follow-on study in software. This study is the first part of a group of studies which will ultimately determine the actual error detection and correction performance of various concatenated coding schemes. Keywords: Computer programs; Assembly language. (Author)