Electrophoretic Image Display with Internal NMOS Address Logic and Display Drivers

摘要

Electrophoretic image displays (EPIDs) exhibit good optical properties, reasonable response times. and very low power consumption. However, the electrophoretic effect is quite linear, thus making standard row-column addressing difficult. This paper presents a practical method for solving pixel addressing by using a custom NMOS VLSI structure as the backplane for the EPID array. A MOSFET per pixel provides the needed threshold effect for X-Y addressing individual pixels. Addition of on-chip shift registers allows serial data entry and line-at-a-time writing of the display panel, and allows expansion of the EP Array without increasing the complexity of the interface circuitry. The design, fabrication, and performance of a prototype 16 x 16 pixel matrix bit map display device is described. These results demonstrate that an NMOS VLSI wafer can be used as the backplane of an EPID, incorporating logic to solve the display addressing problem. In addition, the peripheral areas of the wafer could be utilized for an integrated display processor.