Digit-Pipedlined Arithmetic as Illustrated by the Paste-Up System: A Tutorial

摘要

Data which is digit serial transmitted can result in efficient communication both within and between VLSI chips. Digit serial transmission can be used to an advantage in the design of special purpose processors where communication issues dominate and where digit pipelining can be used to maintain high data rates. VLSI signal processing applications are one such problem domain. We present a family of digit pipelined, digit serial processors. What distinguishes our processors is that the operands are input starting with the most significant digit, where a digit is encoded in a signed-digit, base 4 representation. First, the system conventions are estabished. Then, several of the primitive components are detailed. Each of the primitive components has a latency of one cycle; one cycle after the first operand digits are input the first result digits are output. Finally, several processors which are constructed by combining primitive components according to the system conventions are described.