Static RAM as a Fault Model Evaluator

摘要

This investigation considers the relationship between the physical failures that occur during fabrication and the resulting faulty behavior of the circuit. Fault models are used to describe the operation of integrated circuits containing physical failures introduced during fabrication. The effectiveness of fault models is dependent upon both the accuracy of the model and the occurrence of the underlying failure mechanism. A specially designed static RAM provides the size, design style, and testability required of a fault model test bed. An actual RAM implementation is described which was used for evaluation of fault models.