Extension to the Multilevel Logic Simulator for Microcomputers

摘要

One of the most time consuming parts of the design process is the debugging of the project. This happens when simple modifications to a circuit require recompilation of the whole circuit. In the CAD tool currently available for digital systems design, compilation is a bottle neck. The VOHL system has an extremely efficient simulator phase and a reasonable but slower compilation phase. This thesis investigates a mechanism for eliminating the need to recompile the complete circuit when small changes are needed.