On-Chip Parallelism of VLSI Circuits.

摘要

Simulation is a bottleneck in VLSL circuit design. Not only are there many simulation runs throughout the design cycle, but each run can take hours or days to complete. One often suggested means of speeding up event -driven simulation is to use multiple processors to exploit the natural parallelism present in the circuit, that is to partition the circuit among multiple processors , with each executing the same algorithm on its portion of the circuit. This approach assumes that there is sufficient activity, or circuit parallelism, in the circuit to keep all of the processors busy. The author used two approaches in this work. First she formulated a model for studying circuit parallelism and the potential speedup of parallel logic-level simulation. Using this model she considered the effect of the choice of timing model and synchronization strategy on speedup. She also investigated the effect of circuit size on parallelism. Additionally, she developed a methodology for measuring circuit parallelism, and used it to determine the parallelism if nine circuits using two different simulators. Empirical measurements have also been used to validate portions of the formal model. (kr)