BM/C3 (Battle Management/Command Control and Communications) Technology (Multi-Grain).

摘要

This report represents a method to assess, reliably and rapidly, the performance of parallel (multi-grain) processing architectures for SDS BM/C3 requirements. The existing tools and approaches for making such estimates are either back-of-the-envelope approach, or high fidelity event driven simulations. The processor sizing software tool PERM (Processor Ensemble Runtime Model) developed in this contract is intended to fill the gap between the extremes of very low fidelity and very high fidelity models. PERM explicity models concurrent use of shared resources (memory, bus bandwidth, etc.) in a deterministic fashion and it provides a natural, menu-driven user interface for the construction of data structures and display of results. The methods in algorithm-to-hardware architecture mapping for parallel processing were demonstrated by mapping the AOA tracking algorithm on to the AOSP hardware as a testcase. Section 1 provides the System Description for PERM. Section 2 is the PERM User's Guide. Section 3 presents the testcase. The performance data generated by PERM was analyzed. A discussion is also provided of the experience using PERM both strengths and weaknesses. Keywords: Battle management; Command control and communications; Parallel processors technology; Processor; Sizing; Automated sizing tools. (JHD)