Performance Evaluation of the Scheme86 and HP (High-Performance) Precision Architectures

摘要

The Scheme86 and the HP Precision Architectures represent different trends in computer processor design. The former uses wide micro-instructions, parallel hardware, and a low latency memory interface. The latter encourages pipelined implementation and visible interlocks. To compare the merits of these approaches, algorithms frequently encountered in numerical and symbolic computation were hand-coded for each architecture. Timings were done in simulators and the results were evaluated to determine the speed of each design. Based on these measurements conclusions were drawn as to which aspects of each architecture are suitable for a high-performance computer. (kr)