Optical Clock Distribution to VLSI Chips.

摘要

Investigations of the use of optical for distributing the clock to a CMOS chip are reported. Two chips were designed, the first incorporating a set of integrated detectors followed by transimpedance amplifiers. The clock was distributed as an optical square wave. The detected clock signals were then amplified, distributed on polysilicon, and applied to digital logic. The chips were fabricated at the MOSIS facility. Testing of this family of chips yielded a maximum clock rate of about 20 MHz. A second chip was designed in which the optical clock was used only to synchronize a series of free-running electronic clocks distributed about the chip. Again the fabrication was performed at MOSIS. While theory and simulations predicted a maximum clock frequency of 100 MHz, it proved impossible to actually lock the clocks, due to nonuniformities in the fabrication parameters across the chip. Future work should aim at modifying the design for greater tolerance to fabrication nonuniformities. (RH)