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ZnO Single Barrier Varistor for Logic Circuits Protection.

机译:用于逻辑电路保护的ZnO单势垒压敏电阻。

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Development of ZnO Single Barrier Varistor under this SBIR program has shown very promising results. The pure ZnO used as a substrate for forming the single barrier varistor was prepared by pressing pure ( 99.99% ) polycrystalline ZnO powder and then sintering at 1550 deg C in air. The as-sintered samples are disk shapes of 2.5 cm diameter and 2 - 4 mm thickness. The density after high temperature sintering is 5.4 - 5.6 gm / cc (approx. 95 - 99 % of theoretical density). Current voltage measurements of the pure as-sintered ZnO disks show very high resistivity at room temperature.

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