Design of Style-V: A Translator to Convert Standard VHDL into a Stylized Form for Automated Microcode Generation.

摘要

This thesis provides an analysis and preliminary design of Style V, a source-to-source computer language translator. Style-V converts IEEE standard VHDL into a special style of VHDL defined for a commercial tool, the Integrated Design Automation System (IDAS). Thirteen mappings between standard VHDL and the IDAS subset were identified. The mappings were analyzed using Domain Analysis and Modern Structured Analysis techniques. Four processes covering several of the mappings were completely analyzed. One mapping to convert CASE statements to IF statements was implemented. Since the IDAS restricts designs to bit logic, a method for representing multilevel logic with bit logic was devised. Unacceptable multiple process architectures were converted to multiple single process architectures which are acceptable to IDAS. The IDAS microcode generator does not recognize user-defined procedures, but in one case, mapping user-defined procedures to IDAS defined procedures was not possible. In general, this problem amounts to showing two programs are functionally equivalent. Exhaustive testing was ruled out since proving two 32-bit adders are equivalent would take over 11 billion years at 100 procedure runs per second. The program equivalence problem was not solved by this thesis. Useful results were obtained, though IDAS failed to work.