Design of Current Mode CMOS Multiple-Valued Circuits.

摘要

We propose an algorithm for the design of multiple-valued current- mode CMOS logic (CMCL) circuits that is based on the cost-table technique. The algorithm is a heuristic search technique (AO* algorithm) applied to an AND-OR tree. It is significantly faster than Exhaustive Search while providing realizations that are almost as good. A new cost-table is also proposed that results in better realizations than obtained with a previous cost-table.