Method for Skew-Free Distribution of Digital Signals Using Matched Variable Delay Lines.

摘要

The ability to distribute signals to all parts of a circuit with precisely controlled and known delays is essential in large, high-speed digital systems. We present a technique by which a signal driver can adjust the arrival time of the signal at the end of the wire using a pair of matched variable delay lines. We show how this idea can be implemented requiring no extra wiring, and how it can be extended to distribute signals skew-free to receivers along the signal run as well as the receiving end. We demonstrate how this scheme can be implemented as part of the pad and scan logic of a VLSI chip.... Clock distribution, Skew compensation, Synchronization, Phase adjustment.