Design of Error Detection Scheme for Class C Service in ATM.

摘要

We present a logical approach to designing an effective and efficient error detection scheme for ATM. We specifically look at providing error protection for the class C service of ATM, which is a connection oriented, variable bit rate service, with no required timing between source and destination. Our resulting scheme is similar to the scheme proposed by the CCITT in AAL 5. We propose to add a 34 bit CRC to each frame. Our proposal also includes a modification of the mechanism for preventing misdirected cells that is used at the ATM layer.