Estimating Task Execution Delay in a Real-Time System via Static Source CodeAnalysis

摘要

In a hard-real-time system, it is critical that application tasks complete theiriterative execution cycles within their allotted time frames. For a highly configurable parallel processing system, there exists an overwhelming set of hardware and software configurations, and it is useful to know a priori if a particular configuration satisfies hard-real-time constraints. This thesis presents an automated timing analysis tool which attempts to accurately characterize the timing behavior of the C3 Fault-Tolerant Parallel Processor (FTPP) developed at the Charles Stark Draper Laboratory. For each application task hosted by the FTPP, this automated tool performs a static source code analysis in an effort to estimate a lower bound on worst case execution delay. Then, using the specified mapping between software tasks and hardware processing sites, the analysis tool integrates the results of the individual task analyses in an effort to account for delays due to operating system overhead. The final portion of the analysis involves a prediction of possible performance failures based upon the given system configuration and the timing deadlines imposed by the FTPP's rate group scheduling paradigm. It is intended that the results of this timing analysis will help the user to develop a system configuration that optimizes throughput while minimizing the risk, of performance failures.