Hybrid-Circuit Tile-Approach Architecture for High-Power Spatial Power-CombinedTransmitters

摘要

A new architecture for spatial power combining is presented. This designaddresses the issues of high reliability thermal management, maximizing combining efficiency, and maximizing graceful degradation. The design has been tested with the construction of a brassboard 4-by-4 subarray at 10 6Hz. The measured results show an EIRP of 25.0 dBW (315 W), output power greater than 4 W, and a dc-to-RF conversion efficiency greater than 18%. jg.