Memory Management in the Tera MTA Computer System

摘要

This paper describes memory scheduling for the Tera MTA (Multi ThreadedArchitecture) computer system. The Tera MTA is intended to support a mixture of large and small tasks running in parallel, and ensure that they all make progress commensurate with their importance. We describe the memory scheduling algorithms used to schedule these tasks fairly. Some of the issues encountered and solutions proposed are novel, due in part to the highly multiprogrammed nature of our architecture. In particular, we present an algorithm for swapping a set of tasks to and from memory that achieves minimal overhead, largely independent of the order in which tasks are swapped.