Parallel Block Implicit Integration Technique for Trajectory Parallelism

摘要

This report describes the evaluation of a Parallel Block Implicit (PBI)integration technique in a simplified missile trajectory. This project was carried out to ascertain the suitability of PBI techniques when modest amounts of parallelism are available; that is, when 3 to 10 processors are allocated per missile trajectory. The PBI technique was first evaluated on a serial mainframe computer before it was implemented in parallel on an INMOS TRANSPUTER with four parallel central processing units. While the serial implementation of the four-node PBI technique indicated that a speedup of a factor of three to four was possible with ideal hardware, in practice only a modest gain (approximately 30 percent) was obtained because of systems-related overhead.