Hardware Implementation of a Desktop Supercomputer for High Performance ImageProcessing

摘要

This report presents a CNN monolithic implementation suitable for Very LargeScale Integration. Novel circuit techniques have been investigated, designed and tested for various basic building blocks such as: (1) a transconductance multiplier, (2) a linear resistor based on a multiplier circuit, (3) an OTA based integrator, (4) a hard limiter circuit and (5) YO circuitry based on Switched Capacitor Techniques. The report addresses both circuit design and layout plan issue It highlights also the trade-offs among different design parameters including power supplies, dynamic range, area and tolerance. The CNN cell consumes approximately 2.5mW of power and occupies around O.25mm2 of area. The IC has been sent for fabrication through MOSIS. Preliminary experimental results of some basic building blocks are encouraging.