High-speed test of SFQ-shift register files using PTL wiring

摘要

We have been developing an SFQ shift register memory, which is one candidate to realize high-throughput and high-density superconductive memories. We have modified our memory architecture in order to adapt it to our SFQ microprocessor, CORE1. The new version of the shift register memory is composed of shift registers with nondestructive readout operation, which have an internal feedback. We have also studied the availability of passive transmission line (PTL) wiring in the memory system at high speed. The tested circuit is a 4-byte shift register file, where four kinds of wiring circuits are used between a decoder and shift registers. We have measured the dependences of the DC bias margin on the operating frequency for all wiring methods, and obtained almost the same dependences, which shows the availability of the PTL wiring in the memory system. We have used the NEC 2.5 kA/cm(2) Nb standard process and the CONNECT cell library. (C) 2004 Elsevier B.V. All rights reserved.