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Fast and accurate inductance and coupling calculation for a multi-layer Nb process

机译:多层Nb工艺的快速准确电感和耦合计算

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摘要

Currently, fabrication processes for superconductive integrated circuits are moving to multiple wiring and shielding layers, some of which are placed below the main ground plane (GP) and device layers. The Advanced Industrial Science and Technology advanced process (ADP2) was the first such multi-layer Nb process with planarized passive transmission line and GP layers below the junction layer, and is at the time of writing still the most developed. This process allows complex circuit designs, and accurate inductance extraction helps to push the boundaries of the layouts possible. We show that the position of ground connections between ground layers influences the inductance of structures for which these GPs act as return path, and that this needs to be accounted for in modelling. However, due to the number of wiring layers and GPs, full layout modelling of large cells causes long calculation times. In this paper we discuss methods with which to reduce model size, and calibrate InductEx calculations using these methods against measured results. We show that model reduction followed by calibration results in fast calculation times while good accuracy is maintained. We also show that InductEx correctly handles coupling between conductors in a multi-layer layout, and how to model layouts to gauge unwanted coupling between power lines and single flux quantum electronics.
机译:当前,超导集成电路的制造工艺正在转移到多个布线和屏蔽层,其中一些位于主接地层(GP)和器件层下方。先进工业科学技术先进工艺(ADP2)是第一个这样的多层Nb工艺,其平坦化的无源传输线和结层下方的GP层,在撰写本文时仍是最先进的工艺。此过程允许进行复杂的电路设计,并且准确的电感提取有助于推动布局的边界。我们表明,接地层之间的接地连接的位置会影响这些GP用作返回路径的结构的电感,这需要在建模中加以考虑。但是,由于布线层和GP的数量,大型单元的完整布局建模会导致较长的计算时间。在本文中,我们讨论了减小模型尺寸的方法,并针对测量结果校准了使用这些方法的InductEx计算。我们表明,模型缩小后进行校准可以缩短计算时间,同时保持较高的精度。我们还展示了InductEx可以正确处理多层布局中导体之间的耦合,以及如何对布局进行建模以衡量电源线和单通量量子电子设备之间的有害耦合。

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