A CMOS POWER AMPLIFIER WITH AN ADAPTIVE BIAS SCHEME FOR MOBILE RADIO FREQUENCY IDENTIFICATION READER APPLICATIONS

摘要

A 900-MHz linear power amplifier with an adaptive bias scheme is fabricated using a 0.25-μm CMOS technology. The power amplifier operates over the range of 860-960 MHz, which is the ultrahigh-frequency band for radio frequency identification (RFID). All matching networks and RF chokes are implemented on a chip. The developed power amplifier provides a 1-dB-gain-compression point (P{sub}(1 dB)) of 27 dBm and a power-added-efficiency (PAE) of 28% at the P{sub}(1 dB). The adaptive bias scheme enables the power amplifier to reduce the quiescent power consumption from 280 to 80 mW by adjusting the gate voltage of power transistors as a function of the input power.