Efficiency‐enhanced Doherty power amplifier using Chireix‐like compensation technology

摘要

Abstract This article presents a novel efficiency‐enhanced Doherty power amplifier (DPA) by using a Chireix‐like compensation technique. This technique introduces a compensation circuit structure at the combiner to offset the phase difference effect of a DPA for enhancing drain efficiency. A DPA based on the proposed structure is fabricated with two 10 W GaN high electron mobility transistor (HEMT) transistors. The fabricated DPA with such proposed compensation structure manifests a measured saturated output power of 43.5 dBm and drain efficiency of 68 to 71 in the frequency range of 3.2 to 3.7 GHz. Forty‐five percent of drain efficiency can be achieved at 6 dB power back‐off. And the adjacent channel leakage ratio (ACLR) is better than −48.6 dBc with digital predistortion.