DEPOSITING CONTROLLED, MATCHED RESISTORS FOR CIRCUIT EDIT OF ANALOG CIRCUITRY

摘要

In a recent silicon debug case, the gain of a radio-frequency (RF) CMOS radio receiver circuit block was found in validation to drop dramatically at certain frequencies. The designers deduced that they had not modeled part of the circuit correctly, causing an imbalance in the direct current (dc) biasing circuity of the local oscillator signal path in the receiver. A metal fix option was proposed that would correct this imbalance by rewiring some polysilicon resistors in the circuit, and, naturally, verification was desired before ordering a respin. The circuit edit required a cut and join at the metal 2 level on an eight-metal copper metallization process, with insufficient room to place both cut and join. The focused ion beam (FIB) circuit edit engineers judged that there would only be a small chance of success. There was the prospect of repeating the edit many times and each time debating, "Did the edit fail, or is the fix concept flawed?" The authors thought hard about how to assist the development team with a circuit edit validation, and to do it quickly. This paper shows how, within the space of a few days, a technique was developed to deposit, characterize, and accurately connect matched resistors as an alternative method to achieve the edit, and how this offered not only a faster and more reliable method but also gave significantly more certainty that the result of the edit was indeed a good model for the intended fix.