FPGA speed improvement mixing multiple gate width routing switches

摘要

The operating speed and packaging density of logic circuits implemented by FPGAs are lower than that of logic circuits implemented by ASICs. Such weak points of FPGAs are almost due to routing switches, therefore its transistor sizing becomes essential. Previous works studied this problem assuming that all the routing switches have uniform gate width. In this work, a new routing architecture is proposed assuming multiple gate widths. Compared with the conventional architecture, critical path delays can be reduced by about 20.