A VLSI implementation of a word recognition system for low-power design

摘要

This paper reports a VLSI implementation of a HMM based speech recognition system for low-power VLSI design. output probability calculation is the most computationally expensive part of continuous HMM (CHMM) based speech recognition. The proposed architecture calculates the output probability with parallel and pipeline processing. It enables to reduce memory access and have high computing efficiency. They are effective in low-power design. We have fabricated a chip of the word speech recognition system based on the proposed architecture. The implemented system can achieve a real time response with lower clock in a middle size vocabulary recognition task (100-1000 words) by using this technique.