Fine-Grain Power-Gated Logic for Asynchronous Circuit Using Partial Charge Reuse

摘要

This report introduces a novel low power logic family, called asynchronous fine grain power gated logic (AFPL). Each pipeline stage in the AFPL circuit is made up of efficient charge recovery logic (ECRL) gate, which carry out the logic part of the stage, and a handshake controller, which handles handshaking with the neighboring stages and provide power to ECRL gates. In the AFPL circuit, ECRL gates acquire power and become alive only when performing useful computations, and idle ECRL gates are not powered and thus have negligible power dissipation. The partial charge reuse (PCR) mechanism can be integrated in the AFPL circuit. With the PCR mechanism, part of the charge on the output nodes of an ECRL gate entering the discharge phase can be reused to charge the output nodes of another ECRL gate about to evaluate, reducing the energy dissipation required to complete the evaluation of an ECRL gate. Moreover, the AFPL-PCR adopts an enhanced C-element, called a Sutherland pull-up pull-down, in its handshake controllers such that an ECRL gate in the AFPL-PCR can enter the sleep mode early once its output has been obtained by the downstream pipeline stage. In order to assess the strength of the proposed AFPL, it is carried out in a Kogge-Stone Adder for performance comparison.