Design And Implementation Of Modified Booth Recoder Using Fused Add Multiply Operator

摘要

Complex arithmetic operations are widely used in Digital Signal Processing (DSP) applications. This paper presents an efficient design of modified booth multiplier and then also implements it. Low-cost finite impulse response (FIR) designs are presented using the concept of faithfully rounded truncated multipliers. In this work, focus on optimizing the design of the fused Add-Multiply (FAM) operator for increasing performance. In this project introduce a structured and efficient recoding technique and explore three different schemes by incorporating them in FAM designs. Comparing them with the FAM designs which use existing recoding schemes, the proposed technique yields considerable reductions in terms of critical delay, hardware complexity and power consumption of the FAM unit.