FOR DIGITAL SYSTEMS, the gap between what we can theoretically manufacture in silicon and what we can realistically design has finally stabilised. This is the direct result of re-use strategies involving successively higher levels of abstraction - cell re-use, succeeded by IP reuse, succeeded, in turn, by sub-system and architecture re-use. Today, the system on chip (SoC) design community is already contemplating chip re-use - tiling several fully verified 'chiplets' onto a single piece of silicon. Sub-100nm CMOS process technologies will continue to make cost-effective implementation of these designs possible. The latest large-scale SoCs are already heterogeneous multi-processor systems, containing an array of CPUs, DSPs, vector processors and hardware accelerators.
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