Efficient hierarchical chaotic image encryption algorithm and itsVLSI realisation

摘要

An efficient hierarchical chaotic image encryption algorithm andits VLSI architecture are proposed. Based on a chaotic system and apermutation scheme, all the partitions of the original image arerearranged and the pixels in each partition are scrambled. Itsproperties of high security, parallel and pipeline processing, and nodistortion are analysed. To implement the algorithm, its VLSIarchitecture with pipeline processing, real-time processing capability,and low hardware cost is designed and the FPGA realisation of its keymodules is given. Finally, the encrypted image is simulated and itsfractal dimension is computed to demonstrate the effectiveness of theproposed scheme