BOX engineering to mitigate negative differential resistance in MFIS negative capacitance FDSOI FET: an analog perspective

摘要

Till date, the existing understanding of negative differential resistance (NDR) is obtained from metal-ferro-metal-insulator-semiconductor (MFMIS) FET, and it has been utilized for both MFMIS and metal-ferro-insulator-semiconductor (MFIS) based NCFETs. However, in MFIS architecture, the ferroelectric capacitance (C (FE)) is not a lumped capacitance. Therefore, for MFIS negative capacitance (NC) devices, the physical explanation which governs the NDR mechanism needs to be addressed. In this work, for the first time, we present the first principle explanation of the NDR effect in MFIS NC FDSOI. We found that the output current variation with the drain to source voltage (V (DS)), (i.e. g (ds)) primarily depends upon two parameters: (a) V (DS) dependent inversion charge gradient ( partial differential n/ partial differential V (DS)); (b) V (DS) sensitive electron velocity ( partial differential v/ partial differential V (DS)), and the combined effect of these two dependencies results in NDR. Further, to mitigate the NDR effect, we proposed the BOX engineered NC FDSOI FET, in which the buried oxide (BOX) layer is subdivided into the ferroelectric (FE) layer and the SiO2 layer. In doing so, the inversion charge in the channel is enhanced by the BOX engineered FE layer, which in turn mitigates the NDR and a nearly zero g (ds) with a minimal positive slope has been obtained. Through well-calibrated TCAD simulations, by utilizing the obtained positive g (ds), we also designed a V (DS) independent constant current mirror which is an essential part of analog circuits. Furthermore, we discussed the impact of the FE parameter (remanent polarization and coercive field) variation on the device performances. We have also compared the acquired results with existing literature on NC-based devices, which justifies that our proposed structure exhibits complete diminution of NDR, thus enabling its use in analog circuit design.