Experimental Investigation of the BDD Optimization Procedure Effect on Combinational CMOS Circuit Energy Consumption

P. N. Bibilo; P. V. Leonchik

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Experimental Investigation of the BDD Optimization Procedure Effect on Combinational CMOS Circuit Energy Consumption

机译：BDD优化程序对组合CMOS电路能耗的影响的实验研究

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摘要

The effect of a minimization procedure of multilayered BDD representations of systems of completely defined Boolean functions on combinational CMOS circuit energy consumption is investigated. The corresponding experiment is described, and the obtained results are analyzed.

机译：研究了完全定义布尔函数的系统的多层BDD表示的最小化过程对组合CMOS电路能耗的影响。描述了相应的实验，并对获得的结果进行了分析。

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《Automatic Control and Computer Sciences》 |2010年第5期|共6页
作者
P. N. Bibilo; P. V. Leonchik;
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原文格式 PDF
正文语种 eng
中图分类自动控制理论;
关键词
Energy consumption; Combinational CMOS circuits; Boolean functions; Binary decision diagrams;

机译：能耗;组合CMOS电路;布尔函数;二进制决策图;

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1. Experimental Investigation of the BDD Optimization Procedure Effect on Combinational CMOS Circuit Energy Consumption [J] . P. N. Bibilo, P. V. Leonchik Automatic Control and Computer Sciences . 2010,第5期

机译：BDD优化程序对组合CMOS电路能耗的影响的实验研究
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4. Power and Energy Consumption of CMOS Circuits: Measurement Methods and Experimental Results [C] . Josep Rius, Alejandro Peidro, Salvadro Manich, International Workshop on Integrated Circuit and System Design . 2003

机译：CMOS电路的功率和能耗：测量方法和实验结果
5. Radiation induced soft error mechanisms in nanoscale CMOS combinational logic circuits. [D] . Dhameliya, Harikrushna Himatbhai. 2011

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7. The Energy-Intensive Testing Sets Selection for Realization of the Increased Power Consumption Mode of the Combinational CMOS Circuits [O] . P.N. Bibilo, I.P. Loginova 2016

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8. Test Procedures and Testable-Design Procedures for CMOS LSI/VLSI Circuits [R] . Reddy, S. M. 1986

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Experimental Investigation of the BDD Optimization Procedure Effect on Combinational CMOS Circuit Energy Consumption

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